In the field of semiconductor device manufacturing, active semiconductor devices such as, for example, transistors are generally manufactured or fabricated through processes commonly known as front end of line (FEOL) technologies. A transistor may be, for example, a field-effect-transistor (FET) and may be more specifically a complementary metal-oxide-semiconductor (CMOS) FET. A FET may also be a p-type dopant doped PFET or an n-type dopant doped NFET. Recently, high-k metal gate (HKMG) semiconductor transistors have been introduced because of their superior performance over conventional poly-based CMOS-FET. In addition, a replacement metal gate (RMG) process has been developed to further enhance the performance of HKMG transistors.
Generally, after structure of a transistor is formed, conductive contacts are formed to connect to source, drain, and/or gate of the transistor to make the transistor fully functional. With the continuous scaling down in device dimension in integrated circuitry, real estate for forming corresponding contacts is also becoming smaller and smaller.
As device dimensions scale, silicide to source-drain resistance (interface resistivity times contact length) increases with the inverse of the source/drain contact length. Silicide to source-drain interface resistivity is determined by the interface doping concentration, which is limited by the doping solid solubility and the barrier height, which itself is determined by the choice of the metal. Known solutions to scaling interface resistivity include using rare earth metals, which have a reduced barrier height to a specific type of carrier, and dopant segregation techniques, which “pile up” dopants at the contact interface in order to increase the electric field at the contact interface, in turn reducing the contact barrier height. Since there is an upper limit to the dopant solubility and a lower limit to the achievable contact barrier height with dopant pile-up techniques (typically zero or near zero), there necessarily exists a limit to the interface resistivity. Also, as the device pitch scales down, so does the contact area, which means that the interface resistivity must scale by at least the same amount in order to preserve the same percent-wise contribution of contact resistance to the total on-state resistance. Eventually, this will no longer be possible, due to the limitations mentioned above, at which point the contact resistance is expected to dominate. Therefore, for a given device dimension, methods to increase the silicide contact area is increasingly critical for future nodes, in light of the need to minimize contact resistance due to the increased role that contact resistance plays in the total on-state resistance in aggressively scaled MOSFETs.